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case sensitivity - VHDL is not case sensitive.

entity - a structure that names the VHDL design entity and its ports. The ports are specified further by their mode and type.

Example:

entity truth_table is port( a, b, c : in std_logic; y : out std_logic); end truth_table;

Created: June 26, 2012 By: R. Dueck

Edited: August 31, 2012 By: John Doe

architecture

port

mode

type

std_logic std_logic_vector

bit bit_vector